FIG. 1 illustrates a typical Synchronous Dynamic Random Access Memory (SDRAM) 10, which could include for example a Double Date Rate (DDRx) SDRAM. Specifically shown is a data bus 11, by which data enters and exits the chip. As is typical, this data bus 11 comprises several signals DQ1-DQn which operate in parallel. On the other end of the data bus 11 is another circuit 12, which could comprise a memory controller, a microprocessor, or any other circuit with which the SDRAM 10 might communicate. Typically, SDRAM 10 and circuit 12 comprise discrete integrated circuits mounted to a printed circuit board, such that data bus 11 comprises traces on that printed circuit board. However, this is not strictly necessary, and SDRAM 10 and circuit 12 could also comprise circuit blocks within a single integrated circuit.
Also evident in FIG. 1 are external power supply connections to the SDRAM 10. Specifically shown are two sets of power supply voltages: Vdd and Vss; and Vddq and Vssq. Each set is isolated from the other: Vdd is isolated within the SDRAM 10 from Vddq, and likewise for Vss and Vssq. As one skilled in the art will recognize, Vdd and Vddq typically comprise a positive voltage (perhaps 1.5V or so; Vdd and Vddq can however differ from one another), while Vss and Vssq comprise a lower potential, which is usually ground (i.e., 0V; again, they can differ). An actual SDRAM 10 would of course have other inputs and outputs as well (e.g., address and control signals), but these are not shown in FIG. 1.
Isolation of the power supply sets allows for each set to power different circuitry blocks within the SDRAM 10. Typically, the Vdd/Vss power supply set powers most of the normal logic circuitry in SDRAM 10, such as the array, decode/driver circuitry, and associated logic. By contrast, the Vddq/Vssq power supply set powers the output driver circuitry 20, at least in part, as shown in FIG. 2. Shown in FIG. 2 are the output paths for the various data output signals (DQ1-DQn), which signals typically terminate at bond pads 13 on the SDRAM 10 before proceeding to the data bus 11. (Further details concerning the circuitry of FIG. 2 can be found in U.S. patent application Ser. No. 12/208,562, filed Sep. 11, 2008, to which the reader is referred).
As can be seen, in each of these output paths, pull up (PU) and pull down (PD) drive signals are used to drive the bond pads 13 to a particular logic level. When the output paths are outputting signals to the pads 13, the PU and PD drive signals will (in the illustrated example) be the same in a given path. Therefore, to drive DQ(1) high for example, PU(1)=PD(1)=logic ‘1.’ To drive DQ(1) low, PU(1)=PD(1)=logic ‘0.’ The drive signals PU<1:n> and PD<1:n> could, however, be complementary in other configurations. In still other configurations, each output data path may need only one driving signal, with one state of that signal directing DQ(x) to go high, and the other state directing DQ(x) to go low.
(Even though the PU and PD drive signals are discussed herein as being tied to the same logic level, one skilled in the art will understand that it can still be useful to have these drive signals split so that each can be independently controlled during times when an output is not being driven to the pads 13. For example, independent assertion of PU and PD can be useful during times when the pad is receiving signals to set a proper termination resistance, an approach sometimes referred to as On-Die Termination. For further details, see Micron Technical Note DDR3 ZQ Calibration (2008) (http://download.micron.com/pdf/technotes/DDR3/TN4102.pdf), which is submitted in an Information Disclosure Statement filed with this application).
Because each of the output signals are transferred off of the SDRAM 10 where they will encounter higher capacitances presented by a printed circuit board for example, it is generally preferred to boost the power of the drive signals by ultimately boosting the power of the signals generated at the pads 13. Accordingly, each of the drive signals is progressively boosted along their output paths to higher power capacities by a series of stages. In FIG. 2, stages a-e comprise serially-connected CMOS inverters, and together these can be called buffer stages, B<1:n>. Stage f comprises serially-connected pull-up or pull-down transistors, and because this stage ultimately acts to output the signal to the pads 13, it can be called the transmitter stage, TX<1:n>. Other types of stages can be used as well. In each successive stage, larger (or wider) transistors are used to increase output current. Thus, stage b is larger than stage a, stage c is larger than stage b, etc.
Successive boosting of the power of the drive signals raises the risk of corrupting of the power supply voltages by noise. Accordingly, it is currently preferred, as shown in FIG. 2, to use two isolated power supply sets, such as the Vdd/Vss and Vddq/Vssq sets. These power supply sets may be unregulated by the SDRAM 10, such that they comprise the externally-asserted supplies discussed earlier with respect to FIG. 1. Or, they may comprise versions of these external supplies internally regulated by the SDRAM 10. In any event, the sets are shown in FIG. 2 and in subsequent figures using the same Vdd/Vss and Vddq/Vssq nomenclature for simplicity, which may comprise either regulated or unregulated supplies.
As shown, the first two stages a and b in the output driver circuitry 20 are powered by the Vdd/Vss power supply set. As mentioned earlier, such a power supply set may be used to power the array and logic circuitry in the SDRAM 10. The last stages c-f in the output driver circuitry 20 are powered from the Vddq/Vssq power supply set, which is usually dedicated to the output driving task. As such, the drive signals pass from one power supply domain (i.e., the Vdd/Vss domain) to another power supply domain (i.e., the Vddq/Vssq domain), which boundary occurs at the dotted line 15 between stages b and c in the example illustrated in FIG. 2.
Through this use of dual power supply sets, noise present on the Vddq/Vssq power supply set, as might result from the high-current switching of data at the later stages in the output paths, is prevented, to some degree, from being transferred to the Vdd/Vss power supply set feeding the remainder of the circuitry on the SDRAM 10. However, while the transition of the drive signals between these power supply domains helps to isolate noise between the domains, the decoupling of these two power supply domains has drawbacks. In particular, decoupling the Vddq/Vssq domain from the Vdd/Vss domain renders the Vddq/Vssq domain more susceptible to switching noise than it would be were the entire SDRAM 10 governed by a single, more-heavily-loaded, power domain. Thus, Vddq/Vssq is more easily perturbed as a result of such switching noise. Such noise can be heavily dependent on the particular logic levels being switched at the bond pads 13 at a given time. For example, the output of all logic ‘1’s (or mostly logic ‘1’s) on DQ<1:n> (‘11111111’), creates a power-intensive situation which might load down and hence create noise on Vddq, while the output of all logic ‘0’ (or mostly logic ‘0’s) on DQ<1:n> (“0000000”) might similarly create or increase noise on Vssq. Furthermore, the transitioning between all ‘1’s and all ‘0’s may be even more problematic in many cases.
Switching noise in the Vddq/Vssq domain creates problems for data integrity, and can interfere with the transmission and reception of data at the SDRAM 10. Moreover, the perceived necessity of using two power domains provides an imperfect solution, and one adding additional complexity. Improved output data path architectures are therefore desired, and this disclosure presents certain improvements.